This invention relates generally to partial instruction recycling in a pipelined microprocessor, and more particularly to providing virtual instruction packets for supporting performance features of a microprocessor during partial instruction recycling.
Speculative execution is performed by some microprocessors to optimize performance. Speculative execution executes subsequent instructions before a first instruction completes in hopes that the early results of the first instruction are resolved to be correct.
Performing speculative execution in conjunction with a recycle mechanism minimizes the effect of execution dependencies. In one example, speculation may be performed on a result of data cache (DCache) access. In the case where the speculation is incorrect (a DCache miss), the instruction is repeated or recycled. This method allows for a performance gain over always stalling the pipeline until the result (e.g. fetched DCache data address) of an operation is known for certain. To recycle the instruction, a side recycle queue maintains a copy of the instruction for pending instructions until the instruction is past a certain recycle point.
For further optimization, partial recycles can be performed on operations of a multicycle instruction. For example, when a reject operation occurs in the middle of processing a multicycle instruction, the rejected operation is repeated from the point of the reject. This advantageous over restarting the entire instruction, and sometimes needed for forward progress, where a multi-cycle instruction may be interrupted/rejected many times during execution. This partial restart can not be supported by the information in the recycle queue which only supports full recycle and would have been removed at this point. The processing elements that are dependent on the instruction information from the recycle queue are unable to operate.
It would be advantageous to be able to maintain instruction information for use by processing elements such as, Address Generation Interlock (AGI) and Reliability, Availability, and Serviceability (RAS) checking.